Intel solves key barrier to building hyper-large AI chips

Intel ↗ 1.45% has disclosed a series of breakthroughs in advanced chip packaging at its Rio Rancho, New Mexico facility, solving a key encapsulation challenge that clears the path for hyper-large chip packages scaling to 24 times the standard reticle size — far beyond what the semiconductor industry has achieved to date.

Cracking the Encapsulation Wall

In announcements published on July 29, Intel Foundry detailed how its engineering teams overcame one of the most stubborn barriers to building ever-larger chip packages: getting underfill material to flow reliably across distances that grow with package size. Currently, the maximum underfill flow distance is around 43mm with Intel's EMIB technology and 22mm with standard designs. At scales of 5x to 10x reticle and beyond, the material must travel much farther while eliminating air pockets that compromise reliability.newsroom.intel+1

Intel's solution employs three coordinated innovations. First, an optimized underfill material with lowered viscosity enables the sealant to travel longer distances without sacrificing mechanical integrity. Second, a redesigned multi-point dispensing strategy improves coverage and reduces effective flow distance. Third, a tuned cure process collapses voids to produce defect-free packages.wccftech

The company validated the approach on several packages aligned with its Hyper-Large Form Factor architecture, including an EMIB-based package exceeding 5x reticle housing 18 dies with 12 HBM memory sites, and a tiled EMIB package beyond 7x reticle — both achieving void-free encapsulation. Intel's roadmap targets packages measuring 240mm by 240mm at 24x reticle size, with panel-level packaging eventually pushing beyond 50x reticle.wccftech

Powering AI at Unprecedented Scale

The Rio Rancho facility, which began as a 25-person operation in 1980, now employs 2,700 workers and leverages technologies including Foveros 3D stacking, EMIB silicon bridges, and the latest EMIB-T variant that delivers power directly through bridge channels to meet the demands of high-bandwidth memory. Packages at this scale are expected to operate at 15 to 25 kilowatts, requiring modular cooling architectures and embedded silicon capacitors providing up to 1 millifarad of local energy storage.newsroom.intel+1

"Some of the customers are coming to us first for advanced packaging," said Katie Prouty, manager of Intel's Fab 9 facility. "When we're successful delivering to those customers, they'll continue to grow their trust and faith in Intel as a foundry."newsroom.intel

Ecosystem Expansion

The packaging push is attracting external partners. Tessolve, a semiconductor services firm, announced a collaboration with Intel Foundry to support EMIB-based advanced package design, having completed an end-to-end design and simulation project. Srini Chinamilli, Tessolve's co-founder and CEO, said the partnership allows the company "to further expand our offerings for Intel Foundry customers." Intel also recently announced a collaboration with Lens Technology on glass substrate-based packaging solutions for AI and data center applications.chiplet-marketplace+3